A Comprehensive Hardware Optimization of CNN Architecture through Layer-Specific Enhancement Techniques

초록

This paper presents a comprehensive hardware optimization approach for CNN architecture that addressescomputational efficiency and resource utilization challenges through layer-specific enhancement techniques. Fourmain optimizations are introduced: (1) a processing element-based systolic array structure for the convolutionlayer, (2) a bit-shifter implementation replacing traditional multipliers in the activation layer, (3) a power-awarepipeline design for the fully connected layer, and (4) an efficient floating-point softmax implementation withpipelined exponential operations and parallel accumulation. The experimental results demonstrate significantimprovements across all layers: convolution processing speed achieved a 2.87x increase, activation layer area andpower consumption reduced by 91% and 89.7% respectively, and fully connected layer power consumptiondecreased by 71.4% with minimal area overhead. The proposed softmax implementation provides an efficientsolution for hardware-based probability computation while maintaining numerical stability. These results validatethe effectiveness of this approach in achieving a balanced optimization across different CNN layers whilemaintaining accuracy and providing a complete hardware-oriented solution for CNN implementation.

키워드

Hardware OptimizationCNNProcessing ElementHardware AccelerationPower-Aware PipelineFPGA
제목
A Comprehensive Hardware Optimization of CNN Architecture through Layer-Specific Enhancement Techniques
저자
최범우김영민
발행일
2025-06
유형
Y
저널명
전기전자학회논문지
29
2
페이지
179 ~ 184