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Comparison of hardware accelerator of matrix multiplication with approximate adders
- Chung, Y.;
- Cho, M.;
- Kim, Youngmin
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3초록
Approximate computing is attracting attention as an energy-efficient design, especially suitable for Deep Neural Network and Image Processing. In this study, a variety of approximate adders are applied to a hardware accelerator of 8 by 8 Matrix Multiplication in parallel structure to compare Error Distance and Error Rate. In the simulations, each shows different error figures according to metrics for the reliability, and AMA1, InXA2 and VAXA show the fewest errors according to the indicators. In addition, it shows that various approximate adders have few errors that can be used for matrix multiplication, and that parallel structures and approximate computing can be used appropriately for matrix operations. © 2021 IEEE.
키워드
Approximate adder; Approximate computing; Error distance; Error rate; Hardware accelerator; Adders; Deep neural networks; Energy efficiency; Errors; Image processing; Energy-efficient design; Error distance; Error rate; Hardware accelerators; MAtrix multiplication; Matrix operations; Parallel structures; Matrix algebra
- 제목
- Comparison of hardware accelerator of matrix multiplication with approximate adders
- 저자
- Chung, Y.; Cho, M.; Kim, Youngmin
- 발행일
- 2021
- 유형
- Proceedings Paper
- 저널명
- 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021
- 언어
- ENG
- 출판사
- Institute of Electrical and Electronics Engineers Inc.
- ISSN
- P 0000-0000