Hardware Multi-Threaded System for High-Performance JPEG Decoding

초록

We propose a multi-threaded system that supports reconfigurable hardware accelerators in an embedded computing platform, integrating real-time operating system and CPU-FPGA heterogeneity. Our system focuses on efficient hardware resource management in image signal processing applications, where computational complexities vary in real-time based on data characteristics. Specifically, we implement a high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators, allowing dynamic reconfiguration of up to four accelerators synchronized with software threads. The hardware accelerators are used as hardware threads to compute the 2D-IDCT, which is a computationally intensive task in JPEG decoding. The hardware multi-threaded system integrates software and hardware components, providing seamless interaction between them through the OS services. Our results demonstrate significant performance improvements ranging from approximately 11.00 to 173.96 times when processing 1920 x 1080 compressed images by dynamically adjusting the number of hardware accelerators to provide flexibility and efficient resource utilization. Additionally, we observe that higher resolutions and compression ratios lead to greater performance improvements, leveraging the architectural features of the 2D-IDCT hardware accelerator.

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