A Fast Half Adder using 8T SRAM for Computation-in-Memory

초록

The conventional Von Neumann computing architecture faces limitation as data intensive applications have increased. To solve the problem, the new computing platform "computation-in-memory" has been introduced. In this study, a new design of the half adder implemented in memory array using 8T static random-access memory (SRAM) and latch-type sense amplifier is proposed. This design uses four logic gates to implement a half adder. It reduces time delay of getting the final value by 33% compared to the former architecture of the half adder which uses five logic gates.

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