Efficient Hardware Implementation of Stochastic Computing with Hybrid Techniques

초록

With the development of AI and the increasing size of models, the computational complexity required for processing has grown significantly. From this perspective, Stochastic Computing (SC), which minimizes hardware resources by representing real numbers as the probabilities in bit streams, has garnered attention. In order to maximize the saving of hardware resources, SC techniques that share linearfeedback shift register (LFSR) are being studied, but sharing LFSR directly leads to a decrease in accuracy due to an increase in correlation. To address this issue, this study utilizes hybrid techniques, such as integrating weighted binary generators (WBGs) with comparators (CMPs) and utilizing a bit-shuffling method that combines circular shifting and inverting. Additionally, we propose a novel transition rule that enhances computational accuracy. The proposed hybrid approach and transition rule achieve a 55.6% reduction in power consumption and a 48.6% reduction in area, while maintaining lower error rates than conventional methods. As a result, the figure of merit (FoM) improves by a factor of 4.91. © 2025 IEEE.

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