A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC

초록

A fast lock all-digital programmable N/M -ratio MDLL frequency multiplier using a variable resolution time-to-digital converter (TDC) is presented. The proposed variable resolution TDC measures the initial phase error of the N/M- ratio MDLL and generates the TDC output code required for a fast lock by changing the TDC resolution according to the frequency multiplication factor N. Implemented in a 40-nm CMOS process, the proposed digital MDLL achieves various programmable N/M frequency multiplication ratios of mathbf{N}=1-16 and mathbf{M}=1-8. The MDLL achieves a lock time of about 21 clock cycles ({@}mathbf{N}/mathbf{M}=11/3) and operates over a frequency range of 1-4 GHz. It achieves a peak-to-peak (p-p) jitter of 17 ps and consumes 5.04 mW at 1.16 GHz (mathbf{N}/mathbf{M}=5/3). © 2022 IEEE.

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