Novel 8-bit IMC Approximate Adders with Advanced Error Mitigation Techniques

초록

In this study, we propose novel 8-bit in-memory computing (IMC) approximate adders that enhance the accuracy of conventional 8-bit IMC approximate adders. The conventional structure suffers from high mean error distance (MED) and mean relative error distance (MRED) due to its inability to correct errors stemming from the approximation of the lower 4 bits. In contrast, our novel structures incorporate error reduction units (ERUs) that mitigate errors arising from the approximation of these lower bits. Our results demonstrate a significant reduction in MED (up to 78%) and MRED (up to 74%), as well as an improved error rate (ER) of up to 41% compared to the conventional structure, all while introducing minimal delay. © 2025 IEEE.

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