A 0.8-3.5 GHz shared TDC-based fast-lock all-digital DLL with a built-in DCC

초록

A new time-to-digital converter (TDC)-based fast-lock all-digital delay-locked loop (DLL) with a built-in duty-cycle corrector (DCC) is presented. The proposed DLL utilizes a new shared TDC-based phase correction and duty-cycle correction scheme that results in a fast lock time of less than 22 clock cycles. Conventional DCC embedded DLLs usually have a limited operation frequency and slow lock time. However, in the proposed new architecture, since the DCC is built into the delay line of the DLL, it can operate at high speed of up to 3.5 GHz. Implemented in a 65-nm 1.0V CMOS process, the proposed DLL achieves a frequency range of 0.8-3.5 GHz, and the duty-cycle correction range is ±20% at 0.8 GHz. It achieves an effective p-p output clock jitter of 5.4 ps at 3.5 GHz, occupies an active area of 0.08 mm2, and the power consumption is 8.0 mW at 3.5 GHz. © 2021 IEEE

키워드