A simplified, high-speed, Error-Tolerant Adder using Zero Padding Method

초록

Modern computing operations do not always require accurate operations. Therefore, designing a new approximated adder, although it is not an exact value, obtains higher efficiency in various aspects such as area, power, and speed. The adder proposed in this paper is based on 8 bits, and the higher-order 4 bits use the existing accurate adder, and the lower-order 4 bits approximate with a new method. Compared to the conventional approximate adder, the delay is improved by 19%, and the number of transistors is reduced by 34%, showing higher efficiency than the exact adder. © 2021 IEEE.

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