Low Power Approximate Multiplier Using Error Tolerant Adder

초록

In many applications such as multimedia processing, the power may need to be lowered. Error tolerant adder is used to study carry prediction and approximate multiplication in this paper. The delay of addition between partial products and the results of speculative counters is reduced by the optimized Three-Dimensional Matrix (TDM) suggested in [1] when the speculative counters make no error. The results of the optimized TDM trees are added by the speculative adder for error tolerant computations. The power dissipation is lowered by tolerating the generated errors in the computations deliberately. By the speculative adder, the parts of LSB are approximated in total calculation. Instead of making LSB inaccurate, the total power dissipation is lowered.

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