Novel In-Memory Computing Adder Using 8(+)T SRAM

초록

Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8(+)T SRAM IMC circuit based on 8(+)T differential SRAM (8(+)T SRAM) and proposes 8(+)T SRAM-based IMC full adder (FA) and 8(+)T SRAM-based IMC approximate adder, which are based on the 8(+)T SRAM IMC circuit. The 8(+)T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8(+)T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8(+)T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8(+)T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.

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