Hybrid Assistive Circuit of SRAM for Improving Read and Write Noise Margin in 3nm CMOS

초록

As the demand for low-power devices increases, assist circuits that are more robust to noise at low voltage operation have been used in SRAM. Previous assist circuits have improved performance independently in each operation of read and write. We propose a mixed circuit that can simultaneously increase both RNM and WNM. First, 8T SRAM is used to improve readability, and then CVDD circuits, which control VDD differently depending on operation are added to enhance write noise margin during write operation. As a combination of these two assist circuits, the proposed design provides the 2.94x improvement in the read margin and 1.84x improvement in the write margin compared with the conventional 6T SRAM in 3-nm. © 2022 IEEE.

키워드