Low Power Ternary XNOR using 10T SRAM for In-Memory Computing

초록

To solve the bottleneck of von Neumann architecture, many researchers are looking to in-memory computing as an alternative to overcome this. Similarly, the evolution of neural networks is also emerging as binary neural networks (BNNs) to lower the memory cost. We propose new 10T-bitcell for In-memory Computing, which is capable of ternary multiplication by combining BNN's simple XNOR-based multiplication with the very widely used SRAM. The proposed circuit is simulated at 0.9 V in a 65-nm CMOS process and uses two transistors fewer compared to the conventional ternary multiplication output circuit, and the average power consumption is approximately 2 times lower. © 2022 IEEE.

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