Performance Enhancement of a-IGZO TFTs With Elevated Source/Drain Structure via Channel Trench Etching

초록

We demonstrate an elevated source/drain (S/D) amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) in which the channel is selectively recessed while the S/D access regions retain the original active-layer thickness. Despite sharing the same 10-nm channel thickness as a uniformly thinned device, this structure preserves thick S/D access regions, decoupling gate-control improvement from the access-resistance penalty of uniform active-layer thinning. Transmission-line method (TLM) measurements reveal that the width-normalized contact resistance (R-C & centerdot; W) decreases to 1.04 ohm & centerdot;cm, a 60.2% reduction relative to he uniform 20-nm device. Technology computer-aided design (TCAD) simulations indicate that the decoupled channel-access geometry alleviates current crowding and redistributes the resistive voltage drop. This selective channel trench etching approach offers a simple, interlayerfree route to reducing parasitic resistance in scaled oxide TFTs.

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