A 0.15 to 2.2 GHz All-Digital Delay-Locked Loop

초록

A new harmonic-free, fast-locking, all-digital delay-locked loop (DLL) that uses a lock-in pre-search (LPS) algorithm is presented. By adopting a new LPS algorithm that changes the propagation delay of the coarse delay line (CDL) with five delay steps, the DLL is able to find the approximate locking point before the normal operation. The DLL then performs a binary search and a sequential search to achieve fast locking without the harmonic lock problem. Fabricated in a 0.13-mu m CMOS process, the simple digital DLL architecture achieves a wide frequency range of 0.15-to-2.2 GHz and a measured peak-to-peak clock jitter of 7 ps at 2.2 GHz. It achieves a maximum locking time of only 52 clock cycles, consumes 3.1 mW at 1 GHz from a 1.2 V supply, and occupies an active area of 0.046 mm(2).

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