Efficient Approximate Image Processor with Low-part Stochastic Computing

초록

Stochastic computing with simple logic and error tolerance is a promise paradigm that uses probability values expressed in a serial bitstream. However, stochastic computing has fundamental limitations because it takes longer to convert integers to stochastic numbers, and this has a significant negative impact on power, time, and accuracy. In this paper, we propose a novel approximate adder consisting of an accurate adder for high bits and the unipolar stochastic adder for lower bits. The proposed adder is 22 times more accurate, up to 77% smaller, and reduces significant amounts of required clock cycles compared to a conventional stochastic adder. Then, we apply the proposed architecture to an edge detection and achieve a power reduction (80%) and accuracy improvement (50%).

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