A VLSI design of hierarchical search motion estimation processor chip

Seo, Y.S.; You, J.H.

doi:10.1109/APASIC.1999.824075

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A VLSI design of hierarchical search motion estimation processor chip

Seo, Y.S.;
You, J.H.

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2

초록

This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O bottleneck is eliminated using a small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++ and VHDL. © 1999 IEEE.

제목: A VLSI design of hierarchical search motion estimation processor chip

저자: Seo, Y.S.; You, J.H.

DOI: 10.1109/APASIC.1999.824075

발행일: 1999

유형: Conference Paper

저널명: AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

페이지: 247 ~ 249

언어: ENG

출판사: Institute of Electrical and Electronics Engineers Inc.

분량: 3 페이지

ISSN: P 0000-0000