A Fast-Locking Clock Multiplying DLL

초록

A fast-locking clock multiplying delay-locked loop (MDLL) for fractional-ratio frequency multiplication is presented. A new phase detecting controller (PDC) has been adopted to resolve the long locking time problem of conventional MDLLs. The proposed FMDLL was implemented in 65-nm CMOS process and occupies an active area of 0.015 mm(2). It operates over a frequency range of 2.0-4.0 GHz with a frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while reducing locking time of about 75%.

키워드