An anti-boundary switching fine-resolution digital delay-locked loop

초록

This paper presents a new anti-boundary switching fine-resolution digital delay-locked loop (DLL) for high speed memory systems. The proposed digital DLL uses a new phase-interpolator (PI)-based digitally controlled delay line structure with overlapping period to eliminate the boundary switching problem in conventional digital DLLs, achieving high delay resolution and low jitter characteristics. In addition, by applying the phase inversion scheme and the variable successive approximation register algorithm, the proposed digital DLL achieves a fast locking time of less than 114 cycles and has a wide operating frequency range of 125 MHz-2.7 GHz without producing any harmonic lock problem. Fabricated in a 0.13-A mu m CMOS process, the proposed digital DLL achieves a fine delay resolution of around 2.0 ps and the measured peak-to-peak output clock jitter is only 8.75 ps at 2.7 GHz. The proposed digital DLL occupies an active area of only 0.05 mm(2) and dissipates 8.6 mW of power from a 1.2 V supply at 2.0 GHz.

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