A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line

초록

A novel shared time-to-digital converter (TDC)-based, fast-locking, all-digital delay-locked loop (DLL) incorporating a duty-cycle corrector (DCC)-embedded delay line is introduced. The proposed DLL employs a shared TDC-based structure for both phase locking and duty-cycle correction operations, enabling rapid lock times of approximately 22 clock cycles. The proposed DLL offers the benefit of resolving the delay mismatch issue and achieving a rapid lock time by utilizing a shared delay line structure for both the TDC and the DCC-embedded delay line. This approach allows for high-speed operation up to 3.5 GHz. Implemented using a 65-nm 1.0-V CMOS process, the proposed DLL supports a frequency range from 0.8 to 3.5 GHz, offers a duty-cycle correction range of ±20 % at 0.8 GHz. It achieves an effective peak-to-peak output clock jitter of just 5.4 ps at 3.5 GHz, while maintaining a compact active area of 0.08 mm2 and operating with a power consumption of only 8.0 mW at 3.5 GHz. © 2024 Elsevier Ltd

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