DCT/IDCT Constant Geometry Array Processor for Codec on Display Panel

초록

Algorithms, architectures and 8 X 8 processing element chip design are discussed based on constant geometry 2-Dim. DCT and IDCT. Both DCT and IDCT can be computed with the same hardware for image codec applications. An array of identical PEs is used for butterfly as well as recursive addition stages only with programming of regular interconnections between stages for fault tolerance of system on panel or flexible display panel. Also methodologies to optimize computation speed and amount of required hardware are discussed. An efficient distributed arithmetic ROM for coefficient multiplication is proposed to minimize chip area and to facilitate the PE programming. Chip area, computation time, with image qualities are evaluated with advantages.

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