A High-speed SerDes Transceiver for Wireless Proximity Communication

초록

This paper presents a serializer and deserializer (SerDes) with a phase interpolator (PI) based digital clock and data recovery (CDR) circuit for high-speed and short-range wireless chip-to-chip communication. The SerDes performs 4:1 muxing and 1:4 demuxing functions. The PI-based digital CDR uses an 8-phase delay-locked loop (DLL) to produce a set of evenly spaced reference clock phases. The phase selector performs 2x oversampling to recover the data from the input data signal. Implemented in a 65 nm CMOS process, the proposed SerDes achieves a measured data rate of 10 Gbps and a recovered peak-to-peak clock jitter of 36.25 ps. The SerDes occupies an active area of 0.095 mm(2) and dissipates 88 mW at 10 Gbps.

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