A High-Resolution Wide-Range Dual-Loop Digital Delay-Locked Loop Using a Hybrid Search Algorithm

초록

This paper presents a dual-loop digital delay-locked loop (DLL) for high-speed DRAM applications. The dual-loop architecture using a hybrid (binary + sequential) search algorithm is proposed to achieve both wide-range operation and high delay resolution while maintaining the closed-loop property that allows for tracking of PVT variations. A new phas-einterpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a 0.18-mu m CMOS process, occupies an active area of only 0.19mm(2) and operates over a wide frequency range of 0.15-1.5 GHz. The DLL also dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

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