코오스와 파인 조정을 위한 다이나믹 주파수 스케일링 기법을 사용하는 CMOS 듀티 사이클 보정 회로

초록

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-㎛ CMOS process. The measured duty cycle error is less than ±1.1% for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

키워드