A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory

초록

As the amount of data increases in the era of artificial intelligence (AI), in-memory computing (IMC) circuits are being studied to solve the von Neumann bottleneck, a problem in modern computer architecture. This paper proposes an XOR operator based on 8+T differential static random-access memory (8+T SRAM) and an 8-bit Full-Adder based on it. Simulation results in 65 nm show that the XOR operation is 47% faster than the previous method, the Full-Adder is 43% faster, consumes 32% less energy with 14% less transistor. © 2022 IEEE.

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