A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization

초록

A low-power 20 Gbps multi-phase multiplying delay-locked loop (MDLL)-based clock and data recovery (CDR) with receiver equalization is presented. The proposed MDLL-based digital CDR uses 2x-oversampling technique to lower the bit error rate (BER) and achieves fast lock time using an initial tracking mode. A multi-phase MDLL is utilized to provide the 8-phase reference clocks needed for the P1-based CDR, thereby achieving the power reduction effect. A near-ground signaling (NGS) receiver with a passive CTLE is used for lower power operation at 20 Ghps/channel. The proposed 20 Gbps CDR with receiver equalization is implemented in a 40nm CMOS process, achieving a power consumption of only 25.0 mW (=1.25 mW/Gb/s).

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