Hybrid duty-cycle corrector circuit with dual feedback loop

초록

A two-stage duty amplifier (TDA)-based hybrid duty-cycle corrector (HDCC) circuit with a dual feedback loop is presented. The proposed TDA-based HDCC has improved loop stability and increased isolation as compared to other duty-cycle correctors (DCCs), resulting in a large duty-cycle correction range of up to +/- 30% over a wide frequency range of 0.5-2.0 GHz. It can also support a power-down mode with fast transition to active mode. The measured duty-cycle error is less than +/- 1.49% over an input duty-cycle range of 20-80% for 0.5-2.0 GHz. The HDCC is fabricated in a 0.18 mu m CMOS process and occupies an area of only 0.043 mm(2)