Short Channel 2D FET with Sloped Architecture

초록

The miniaturization of electronic devices remains a primary focus in the semiconductor industry as it directly impacts both performance enhancement and cost reduction. However, achieving extreme scaling down often relies on high-resolution lithography techniques, which are limited by complexity and an intensive processing time. Two-dimensional transition metal dichalcogenides (2D TMDCs) have great potential for developing short-channel field effect transistors (FETs) due to their atomically thin nature and high Young's modulus. Here, the nanometer-scale channel length in a 2D TMDC-based FET is realized by constructing the sloped architecture without lithography techniques. Utilizing h-BN tunneling layers ensures the mitigated short channel effect (SCE), resulting in a high on-off ratio and low subthreshold swing (SS). This sloped architecture short channel FET (SSFET) exhibits an on-off ratio over 10(5) with an SS of 160 mV/dec and an on-current level of 3.70 mu A. This new approach can provide an innovative pathway to realize the nanometer-scale FET without complicating fabrication processes.

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