Design and implementation of ternary carry lookahead adder on FPGA

Park, J.; Kim, Youngmin

doi:10.1109/ICEIC51217.2021.9369710

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Design and implementation of ternary carry lookahead adder on FPGA

Park, J.;
Kim, Youngmin

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초록

Ternary value logic (TVL) has advantages over binary system, such as providing smaller chip area and faster computation speed. However, ternary hardware implementation is in theoretical, simulation levels. Moreover, no hardware description language for ternary logic is developed. In this paper, by representing 1 trit (trinary digit) with 2 bit, ternary logic is implemented and analyzed in FPGA. To specify the performance of TVL, ternary carry lookahead adder is implemented on FPGA and the speed and power dissipation of the arithmetic unit are measured. The performance of 21-trit ternary CLA is compared with 32-bit binary CLA. The results show that ternary CLA is faster up to 10.36% and consumes 13.54% less power than binary CLA. In addition, performances of ripple carry adder using both ternary and binary logic are simulated. © 2021 IEEE.

키워드

Carry lookahead adder; FPGA; Multi-valued logic; Ternary ALU; Adders; Computation theory; Computer circuits; Computer hardware description languages; Field programmable gate arrays (FPGA); Integrated circuit design; Arithmetic unit; Binary systems; Carry look-ahead adder; Computation speed; Design and implementations; Hardware implementations; Ripple carry adders; Ternary logic; Carry logic

제목: Design and implementation of ternary carry lookahead adder on FPGA

저자: Park, J.; Kim, Youngmin

DOI: 10.1109/ICEIC51217.2021.9369710

발행일: 2021

유형: Proceedings Paper

저널명: 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

언어: ENG

출판사: Institute of Electrical and Electronics Engineers Inc.

ISSN: P 0000-0000