Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source-Drain Resistances in MOSFETs

  • Bae, Hagyoul; 
  • Jang, Jaeman; 
  • Shin, Ja Sun; 
  • Yun, Daeyoun; 
  • Lee, Jieun; 
  • ... Kim, Tae Wan; 
  • 외 2명
Citations

WEB OF SCIENCE

13
Citations

SCOPUS

14

초록

A new technique for a separate extraction of the current-path-dependent resistance (R(SD0)) from the contact-dependent source and drain resistances (R(Se) and R(De)) is reported for a single MOSFET. We also report a technique for a separation of V(GS)-dependent source and drain resistance (R(SDi)) from the V(GS)- and L(eff)-dependent channel resistance (R(ch)) with multiple MOSFETs. We confirm the proposed techniques applied to n-channel MOSFETs with various W/L combinations and obtain R(Se) = 10.5-12.4 Omega, R(De) congruent to 12.7 Omega, and R(SD0) = 4.7 Omega for W = 10 mu m. V(GS)-dependent but L-independent R(SDi) is extracted to be 2.8-4.2 Omega.

키워드

Drain resistance; extraction; extrinsic; intrinsic resistance; MOSFET; parasitic resistance; source resistance; SERIES RESISTANCE; LDD MOSFETS
제목
Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source-Drain Resistances in MOSFETs
저자
Bae, Hagyoul; Jang, Jaeman; Shin, Ja Sun; Yun, Daeyoun; Lee, Jieun; Kim, Tae Wan; Kim, Dae Hwan; Kim, Dong Myong
DOI
10.1109/LED.2011.2131116
발행일
2011-06
유형
Article
저널명
IEEE Electron Device Letters
권
32
호
6
페이지
722 ~ 724