Bias-stress-induced trapping effect of high-voltage field-plated AlGaN/GaN-on-Si heterostructure FETs

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초록

AlGaN/GaN heterostructure field effect transistors (HFETs) with a gate field plate were fabricated on GaN-on-Si substrates. Devices demonstrated high breakdown voltages over 500 V for high-voltage switching operation. We applied a DC stress under on-state and off-state conditions to investigate the degradation characteristics. Degradations of the output and the transfer characteristics were observed after stress tests and recovered after 10 days in ambient storage. The electron trapping effect played a major role in the observed degradations. We also observed a correlation between the field-plate length and the degradation. The technology computer aided design (TCAD) simulation indicated that this dependence could be attributed to a change in the electric field distribution in the channel that depended on the field-plate dimension.

키워드

Channel temperature; DC stress; Electron trapping; Field plate; GaN; High voltage; Inverse piezoelectric effect; Reliability; HIGH-ELECTRIC-FIELD; RELIABILITY; HEMT; RF
제목
Bias-stress-induced trapping effect of high-voltage field-plated AlGaN/GaN-on-Si heterostructure FETs
저자
Choi, Shinhyuk; Lee, Jae-Gil; Cha, Ho-Young; Kim, Hyungtak
DOI
10.3938/jkps.62.954
발행일
2013-03
유형
Article
저널명
Journal of the Korean Physical Society
권
62
호
6
페이지
954 ~ 958