A Programmable Delay-Locked Loop Based Clock Multiplier

초록

This paper presents a programmable delay-locked loop (DLL) based clock multiplier that provides flexible integer clock multiplication for high-performance clocking applications. The proposed DLL-based clock multiplier removes harmonic lock and stuck problems, which allows changing of the input clock frequency and multiplication factor during operation without any external reset. The output frequency range is from 195 MHz to 1.0 GHz with a multiplication factor N = 4, 5, 8, 10, 16, and 20. The proposed clock multiplier, implemented in a 0.18-mu m 1.8-V CMOS process, occupies an active area of only 0.14 mm(2). This clock multiplier achieves a measured rms and peak-to-peak jitter of 7.11ps and 30.0ps at 1.0 GHz, respectively.

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