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자료 필터
자료유형
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2008 ~ 2025
2008 2025
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전체 70건 중 21번부터 30번까지의 결과를 표시합니다.
2019
Article
A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization
- Hwang, Heejae ;
- Kim, Jongsun
- 2019
- 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)
- IEEE
Article
A low-power 20 Gbps multi-phase MDLL-based digital CDR with receiver equalization
- Hwang, H. ;
- Kim, J.
- 2019
- Proceedings - 2019 International SoC Design Conference, ISOCC 2019
- Institute of Electrical and Electronics Engineers Inc.
2018
Article
A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks
- 2018-12
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- IEEK PUBLICATION CENTER
Article
An anti-boundary switching fine-resolution digital delay-locked loop
- 2018-09
- Analog Integrated Circuits and Signal Processing
- SPRINGER
Article
A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs
- Kim, Jongsun ;
- Han, S. W.
- 2018-04-10
- IEICE Electronics Express
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Article
An anti-harmonic MDLL for phase-aligned on-chip clock multiplication
- Kim, Jongsun ;
- Bae, B. H.
- 2018-03-10
- IEICE Electronics Express
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Article
A High-speed SerDes Transceiver for Wireless Proximity Communication
- Kim, Jongsun ;
- Kim, Jintae
- 2018-02
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- IEEK PUBLICATION CENTER
2017
Article
An All-digital Delay-locked Loop using a Lock-in Pre-search Algorithm for High-speed DRAMs
- 2017-12
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- IEEK PUBLICATION CENTER
Article
A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs
- Yoon, Junsub ;
- Heo, Seo Weon ;
- Kim, Jongsun
- 2017-01-25
- IEICE Electronics Express
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG